CS101 532 CS201 225 CS301 232 CS302 174 CS304 192 CS401 224 CS402 258 CS403 228 CS408 113 CS411 121 CS502 249 CS504 268 CS601 679 CS604 381 CS605 261 CS607 184 CS609 230 CS610 300 CS614 100 CS703 65
Code Question Option A Option B Option C Option D Answer
CS302 __________ Counters As The Name Indicates Are Not Triggered Simultaneously Asynchronous Synchronous Positive-Edge Triggered Negative-Edge Triggered A
CS302 __________ Is Invalid Number Of Cells In A Single Group Formed By The Adjacent Cells In K-Map 2 8 12 16 C
CS302 __________ Is One Of The Examples Of Asynchronous Inputs J-K Input S-R Input D Input Clear Input (Clr) D
CS302 __________ Is One Of The Examples Of Synchronous Inputs J-K Input En Input Preset Input (Pre) Clear Input (Clr) A
CS302 __________ Is Said To Occur When Multiple Internal Variables Change Due To Change In One Input Variable Clock Skew Race Condition Hold Delay Hold And Wait B
CS302 __________ Is Used To Minimize The Possible No. Of States Of A Circuit State Assignment State Reduction Next State Table State Diagram A
CS302 __________ Is Used To Simplify The Circuit That Determines The Next State State Diagram Next State Table State Reduction State Assignment D
CS302 __________Occurs When The Same Clock Signal Arrives At Different Times At Different Clock Inputs Due To Propagation Delay Race Condition Clock Skew Ripple Effect None Of Given Options B
CS302 3.3 V Cmos Series Is Characterized By __________ And ___________As Compared To The 5 V Cmos Series Low Switching Speeds High Power Dissipation Fast Switching Speeds High Power Dissipation Fast Switching Speeds Very Low Power Dissipation Low Switching Speeds Very Low Power Dissipation C
CS302 3-To-8 Decoder Can Be Used To Implement Standard Sop And Pos Boolean Expressions True False A
CS302 5-Bit Johnson Counter Sequences Through States 7 10 32 25 B
CS302 74Hc163 Has Two Enable Input Pins Which Are And ___________ Enp Ent Eni Enc Enp Enc Ent Eni A
CS302 A + B = B + A Is __________ Demorgan"S Law Distributive Law Commutative Law Associative Law C
CS302 A 4-Bit Binary Up/Down Counter Is In The Binary State Zero. The Next State In The Down Mode Is__________ 0001 1111 1000 1110 B
CS302 A 8-Bit Serial In / Parallel Out Shift Register Contains The Value “8” Clock Signal(S) Will Be Required To Shift The Value Completely Out Of The Register 1 2 4 8 D
CS302 A Counter Is Implemented Using Three (3) Flip-Flops Possibly It Will Have __________ Maximum Output Status 3 7 8 15 C
CS302 A Decade Counter Can Be Implemented By Truncating The Counting Sequence Of A Mod-20 Counter True False A
CS302 A Decade Counter Is __________ Mod-3 Counter Mod-5 Counter Mod-8 Counter Mod-10 Counter D
CS302 A Decade Counter Is __________ Mod-3 Counter Mod-5 Counter Mod-8 Counter Mod-10 Counter D
CS302 A Divide-By-50 Counter Divides The Input Signal To A 1 Hz Signal 10 Hz 50 Hz 100 Hz 500 Hz B