|
CS302
|
If Two Adjacent 1S Are Detected In The Input The Output Is Set To High
|
0011
|
0101
|
1100
|
1010
|
A
|
|
CS302
|
__________Occurs When The Same Clock Signal Arrives At Different Times At Different Clock Inputs Due To Propagation Delay
|
Race Condition
|
Clock Skew
|
Ripple Effect
|
None Of Given Options
|
B
|
|
CS302
|
The Decimal “17” In Bcd Will Be Represented As ___________
|
11101
|
11011
|
10111
|
11110
|
C
|
|
CS302
|
If The S And R Inputs Of The Gated S-R Latch Are Connected Together Using A Gate Then There Is Only A Single Input To The Latch. The Input Is Represented By D Instead Of S Or R (A Gated D-Latch)
|
And
|
Or
|
Not
|
Xor
|
C
|
|
CS302
|
Don’T Care Conditions Are Marked As __________ In The Output Column Of The Function Table
|
0
|
1
|
X
|
None Of The Given Options
|
C
|
|
CS302
|
Determine The Values Of A B C And D That Make The Sum Term A(Bar) + B+C(Bar)+D Equal To Zero
|
A = 1 B = 0 C = 0 D = 0
|
A = 1 B = 0 C = 1 D = 0
|
A = 0 B = 1 C = 0 D = 0
|
A = 1 B = 0 C = 1 D = 1
|
B
|
|
CS302
|
For A Positive Edge-Triggered J-K Flip-Flop With Both J And K High The Outputs Will If The Clock Goes High
|
Toggle
|
Set
|
Reset
|
Not Change
|
A
|
|
CS302
|
What Is The Difference Between A D Latch And A D Flip-Flop?
|
The D Latch Has A Clock Input
|
The D Flip-Flop Has An Enable Input
|
The D Latch Is Used For Faster Operation
|
The D Flip-Flop Has A Clock Input
|
D
|
|
CS302
|
How Many Data Select Lines Are Required For Selecting Eight Inputs?
|
1
|
2
|
3
|
4
|
C
|
|
CS302
|
The Synchronous Counters Are Also Known As Ripple Counters
|
True
|
False
|
|
|
B
|
|
CS302
|
The Best State Assignment Tends To __________
|
Maximizes The Number Of State Variables That Don’T Change In A Group Of Related States
|
Minimizes The Number Of State Variables That Don"T Change In A Group Of Related States
|
Minimize The Equivalent States
|
None Of Given Options
|
A
|
|
CS302
|
Dram Stands For __________
|
Dynamic Ram
|
Data Ram
|
Demoduler Ram
|
None Of Given Options
|
A
|
|
CS302
|
In __________ All The Columns In The Same Row Are Either Read Or Written
|
Sequential Access
|
Mos Access
|
Fast Mode Page Access
|
None Of Given Options
|
C
|
|
CS302
|
We Have A Digital Circuit. Different Parts Of Circuit Operate At Different Clock Frequencies (4Mhz 2Mhz And 1Mhz) But We Have A Single Clock Source Having A Fix Clock Frequency (4Mhz) We Can Get Help By __________
|
Using S-R Flop-Flop
|
D-Flipflop
|
J-K Flip-Flop
|
T-Flip-Flop
|
C
|
|
CS302
|
A Logic Circuit With An Output Consists Of __________
|
Two And Gates Two Or Gates Two Inverters
|
Three And Gates Two Or Gates One Inverter
|
Two And Gates One Or Gate Two Inverters
|
Two And Gates One Or Gate
|
C
|
|
CS302
|
Stack Is An Acronym For ___________
|
Fifo Memory
|
Lifo Memory
|
Flash Memory
|
Bust Flash Memory
|
B
|
|
CS302
|
The Power Dissipation Pd Of A Logic Gate Is The Product Of The
|
Dc Supply Voltage And The Peak Current
|
Dc Supply Voltage And The Average Supply Current
|
Ac Supply Voltage And The Peak Current
|
Ac Supply Voltage And The Average Supply Current
|
A
|
|
CS302
|
A + B = B + A Is __________
|
Demorgan"S Law
|
Distributive Law
|
Commutative Law
|
Associative Law
|
C
|
|
CS302
|
A Frequency Counter __________
|
Counts Pulse Width
|
Counts No. Of Clock Pulses In 1 Second
|
Counts High And Low Range Of Given Clock Pulse
|
None Of Given Options
|
B
|
|
CS302
|
The Abel Symbol For “Or” Operation Is
|
!
|
&
|
#
|
$
|
C
|