|
CS302
|
A Nibble Consists Of Bits
|
2
|
4
|
8
|
16
|
B
|
|
CS302
|
Rco Stands For ___________
|
Reconfiguration Counter Output
|
Reconfiguration Clock Output
|
Ripple Counter Output
|
Ripple Clock Output
|
D
|
|
CS302
|
When Both The Inputs Of Edge-Triggered J-K Flop-Flop Are Set To Logic Zero ___________
|
The Flop-Flop Is Triggered
|
Q=0 And Q"=1
|
Q=1 And Q’=0
|
The Output Of Flip-Flop Remains Unchanged
|
C
|
|
CS302
|
A Positive Edge-Triggered Flip-Flop Changes Its State When ____________________
|
Low-To-High Transition Of Clock
|
High-To-Low Transition Of Clock
|
Enable Input (En) Is Set
|
Preset Input (Pre) Is Set
|
A
|
|
CS302
|
A Standard Sop Form Has __________ Terms That Have All The Variables In The Domain Of The Expression
|
And
|
Or
|
Sum
|
Not
|
C
|
|
CS302
|
Sum Term (Max Term) Is Implemented Using __________ Gates
|
Or
|
And
|
Not
|
Or-And
|
A
|
|
CS302
|
For A Gated D-Latch If En=1 And D=1 Then Q(T+1) =
|
0
|
1
|
Q(T)
|
Invalid
|
D
|
|
CS302
|
The 4-Variable Karnaugh Map (K-Map) Has Rows And Colums
|
2 2
|
4 4
|
4 2
|
2 4
|
B
|
|
CS302
|
The Design And Implementation Of Synchronous Counters Start From ___________
|
Truth Table
|
K-Map
|
State Table
|
State Diagram
|
D
|
|
CS302
|
The Address From Which The Data Is Read Is Provided By
|
Depends On Circuitry
|
None Of Given Options
|
Ram
|
Microprocessor
|
D
|
|
CS302
|
__________ Is Invalid Number Of Cells In A Single Group Formed By The Adjacent Cells In K-Map
|
2
|
8
|
12
|
16
|
C
|
|
CS302
|
The Sequence Of States That Are Implemented By A N-Bit Johnson Counter Is
|
N+2 (N Plus 2)
|
2N (N Multiplied By 2)
|
2N (2 Raise To Power N)
|
N2 (N Raise To Power 2)
|
B
|
|
CS302
|
__________ Is One Of The Examples Of Asynchronous Inputs
|
J-K Input
|
S-R Input
|
D Input
|
Clear Input (Clr)
|
D
|
|
CS302
|
The ___________ Of A Rom Is The Time It Takes For The Data To Appear At The Data Output Of The Rom Chip After An Address Is Applied At The Address Input Lines
|
Write Time
|
Recycle Time
|
Refresh Time
|
Access Time
|
D
|
|
CS302
|
A 8-Bit Serial In / Parallel Out Shift Register Contains The Value “8” Clock Signal(S) Will Be Required To Shift The Value Completely Out Of The Register
|
1
|
2
|
4
|
8
|
D
|
|
CS302
|
In __________ Outputs Depend Only On The Combination Of Current State And Inputs
|
Mealy Machine
|
Moore Machine
|
State Reduction Table
|
State Assignment Table
|
A
|
|
CS302
|
A Field-Programmable Logic Array Can Be Programmed By The User And Not By The Manufacturer
|
True
|
False
|
|
|
A
|
|
CS302
|
In The Q Output Of The Last Flip-Flop Of The Shift Register Is Connected To The Data Input Of The First Flip-Flop
|
Moore Machine
|
Meally Machine
|
Johnson Counter
|
Ring Counter
|
C
|
|
CS302
|
In Designing Any Synchronous Counter A Modulus Number Is Used Which Determine The Number Of............ Used In A Counter
|
Registers
|
Flip Flops
|
Counters
|
Latches
|
B
|
|
CS302
|
Divide-By-160 Counter Is Acheived By Using
|
Flip-Flop And Div 10
|
Flip-Flop And Div 16
|
Div 16 And Div 32
|
Div 16 And Div 10
|
C
|