CS101
532
CS201
225
CS301
232
CS302
174
CS304
192
CS401
224
CS402
258
CS403
228
CS408
113
CS411
121
CS502
249
CS504
268
CS601
679
CS604
381
CS605
261
CS607
184
CS609
230
CS610
300
CS614
100
CS703
65
| Code | Question | Option A | Option B | Option C | Option D | Answer | |
|---|---|---|---|---|---|---|---|
| CS302 | A Synchronous Decade Counter Will Have Flip-Flops | 3 | 4 | 7 | 10 | A | |
| CS302 | A Transparent Mode Means __________ | The Changes In The Data At The Inputs Of The Latch Are Seen At The Output | The Changes In The Data At The Inputs Of The Latch Are Not Seen At The Output | Propagation Delay Is Zero (Output Is Immediately Changed When Clock Signal Is Applied) | Input Hold Time Is Zero (No Need To Maintain Input After Clock Transition) | A | |
| CS302 | Addition Of Two Octal Numbers “36” And “71” Results In __________ | 213 | 123 | 127 | 345 | C | |
| CS302 | An Alternate Method Of Implementing Comparators Which Allows The Comparators To Be Easily Cascaded Without The Need For Extra Logic Gates Is | Using A Single Comparator | Using Iterative Circuit Based Comparators | Connecting Comparators In Vertical Hierarchy | Extra Logic Gates Are Always Required | B | |
| CS302 | An Astable Multivibrator Is Known As A(N) | Oscillator | Booster | One-Shot | Dual-Shot | C | |
| CS302 | An Example Of Sop Expression Is | A + B(C + D) | A B + Ac + Ab C | (A + B + C)(A + B + C) | Both (A) Nad (B | D | |
| CS302 | Assume That A 4-Bit Serial In/Serial Out Shift Register Is Initially Clear. We Wish To Store The Nibble 1100. What Will Be The 4-Bit Pattern After The Second Clock Pulse? (Right-Most Bit First.) | 1100 | 0011 | 0000 | 1111 | C | |
| CS302 | Asynchronous Mean That__________ | Each Flip-Flop After The First One Is Enabled By The Output Of The Preceding Flip-Flop | Each Flip-Flop Is Enabled By The Output Of The Preceding Flip-Flop | Each Flip-Flop Except The Last One Is Enabled By The Output Of The Preceding Flip-Flop | Each Alternative Flip-Flop After The First One Is Enabled By The Output Of The Preceding Flip-Flop | D | |
| CS302 | At T0 The Value Stored In A 4-Bit Left Shift Was “1”. What Will Be The Value Of Register After Three Clock Pulses? | 2 | 4 | 6 | 8 | D | |
| CS302 | Bi-Stable Devices Remain In Either Of Their ___________ States Unless The Inputs Force The Device To Switch Its State | Ten | Eight | Three | Two | D | |
| CS302 | Bi-Stable Devices Remain In Either Of Their States Unless The Inputs Force The Device To Switch Its State | 10 | 8 | 3 | 2 | D | |
| CS302 | Caveman Number System Is Base Number System | 2 | 5 | 10 | 16 | B | |
| CS302 | Consider A=1 B=0 C=1. A B And C Represent The Input Of Three Bit Nand Gate The Output Of The Nand Gate Will Be | Zero | One | Undefined | No Output As Input Is Invalid | B | |
| CS302 | Demultiplexer Converts Data To __________ Data | Parallel Data Serial Data | Serial Data Parallel Data | Encoded Data Decoded Data | All Of The Given Options | B | |
| CS302 | Demultiplexer Is Also Called | Data Selector | Data Router | Data Distributor | Data Encoder | C | |
| CS302 | Determine The Values Of A B C And D That Make The Sum Term A(Bar) + B+C(Bar)+D Equal To Zero | A = 1 B = 0 C = 0 D = 0 | A = 1 B = 0 C = 1 D = 0 | A = 0 B = 1 C = 0 D = 0 | A = 1 B = 0 C = 1 D = 1 | B | |
| CS302 | Divide-By-160 Counter Is Acheived By Using | Flip-Flop And Div 10 | Flip-Flop And Div 16 | Div 16 And Div 32 | Div 16 And Div 10 | C | |
| CS302 | Don’T Care Conditions Are Marked As __________ In The Output Column Of The Function Table | 0 | 1 | X | None Of The Given Options | C | |
| CS302 | Dram Stands For __________ | Dynamic Ram | Data Ram | Demoduler Ram | None Of Given Options | A | |
| CS302 | Excess-8 Code Assigns To “+7” | 0000 | 1001 | 1000 | 1111 | A |