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CS302
|
__________ Is Used To Minimize The Possible No. Of States Of A Circuit
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State Assignment
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State Reduction
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Next State Table
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State Diagram
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A
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CS302
|
A Flip-Flop Is Connected To +5 Volts And It Draws 5 Ma Of Current During Its Operation The Power Dissipation Of The Flip-Flop Is
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10 Mw
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25 Mw
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64 Mw
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1024
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B
|
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CS302
|
Demultiplexer Is Also Called
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Data Selector
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Data Router
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Data Distributor
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Data Encoder
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C
|
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CS302
|
The Expression F=A+B+C Describes The Operation Of Three Bits Gate
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Or
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And
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Not
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Nand
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A
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CS302
|
The Voltage Gain Of The Inverting Amplifier Is Given By The Relation __________
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Vout / Vin = - Rf / Ri
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Vout / Rf = - Vin / Ri
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Rf / Vin = - Ri / Vout
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Rf / Vin = Ri / Vout
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A
|
|
CS302
|
The Divide-By-60 Counter In Digital Clock Is Implemented By Using Two Cascading Counters
|
Mod-6 Mod-10
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Mod-50 Mod-10
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Mod-10 Mod-50
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Mod-50 Mod-6
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A
|
|
CS302
|
Assume That A 4-Bit Serial In/Serial Out Shift Register Is Initially Clear. We Wish To Store The Nibble 1100. What Will Be The 4-Bit Pattern After The Second Clock Pulse? (Right-Most Bit First.)
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1100
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0011
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0000
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1111
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C
|
|
CS302
|
A Decade Counter Is __________
|
Mod-3 Counter
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Mod-5 Counter
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Mod-8 Counter
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Mod-10 Counter
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D
|
|
CS302
|
If S=1 And R=1 Then Q(T+1) = ___________ For Negative Edge Triggered Flip-Flop
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0
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1
|
Invalid
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Input Is Invalid
|
C
|
|
CS302
|
The Binary Numbers A = 1100 And B = 1001 Are Applied To The Inputs Of A Comparator. What Are The Output Levels?
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A > B = 1 A < B = 0 A < B = 1
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A > B = 0 A < B = 1 A = B = 0
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A > B = 1 A < B = 0 A = B = 0
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A > B = 0 A < B = 1 A = B = 1
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C
|
|
CS302
|
The Basic Building Block For A Logical Circuit Is
|
A Flip-Flop
|
A Logical Gate
|
An Adder
|
None Of Given Options
|
B
|
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CS302
|
Nand Gate Is Formed By Connecting ___________
|
And Gate And Then Not Gate
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Not Gate And Then And Gate
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And Gate And Then Or Gate
|
Or Gate And Then And Gate
|
A
|
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CS302
|
A Divide-By-50 Counter Divides The Input Signal To A 1 Hz Signal
|
10 Hz
|
50 Hz
|
100 Hz
|
500 Hz
|
B
|
|
CS302
|
In __________ Outputs Depend Only On The Current State
|
Mealy Machine
|
Moore Machine
|
State Reduction Table
|
State Assignment Table
|
B
|
|
CS302
|
A Transparent Mode Means __________
|
The Changes In The Data At The Inputs Of The Latch Are Seen At The Output
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The Changes In The Data At The Inputs Of The Latch Are Not Seen At The Output
|
Propagation Delay Is Zero (Output Is Immediately Changed When Clock Signal Is Applied)
|
Input Hold Time Is Zero (No Need To Maintain Input After Clock Transition)
|
A
|
|
CS302
|
In Designing Any Counter The Transition From A Current State To The Next Sate Is Determined By
|
Current State And Inputs
|
Only Inputs
|
Only Current State
|
Current State And Outputs
|
A
|
|
CS302
|
The Complement Of A Variable Is Always
|
0
|
1
|
Equal To The Variable
|
The Inverse Of The Variable
|
D
|
|
CS302
|
Q2 :=Q1 Or X Or Q3 The Above Abel Expression Will Be
|
Q2:= Q1 $ X $ Q3
|
Q2:= Q1 # X # Q3
|
Q2:= Q1 & X & Q3
|
Q2:= Q1 ! X ! Q3
|
B
|
|
CS302
|
The Output Of An Xnor Gate Is 1 When __________ I) All The Inputs Are Zero Ii) Any Of The Inputs Is Zero Iii) Any Of The Inputs Is One Iv) All The Inputs Are One
|
I Only
|
Iv Only
|
I And Iv Only
|
Ii And Iii Only
|
D
|
|
CS302
|
The Three Fundamental Gates Are __________
|
And Nand Xor
|
Or And Nand
|
Not Nor Xor
|
Not Or And
|
D
|