Online Exam Preparation
MCQs Library
Browse subject-wise multiple choice questions, review answers quickly, and start a test from the same section.
Questions
| Code | Question | Option A | Option B | Option C | Option D | Answer |
|---|---|---|---|---|---|---|
| CS302 |
Excess-8 Code Assigns To “-8”
|
1110
|
1100
|
1000
|
0000
|
D |
| CS302 |
Fifo Is An Acronym For __________
|
First In First Out
|
Fly In Fly Out
|
Fast In Fast Out
|
None Of Given Options
|
A |
| CS302 |
Flip Flops Are Also Called __________
|
Bi-Stable Dualvibrators
|
Bi-Stable Transformer
|
Bi-Stable Multivibrators
|
Bi-Stable Singlevibrators
|
C |
| CS302 |
For A Down Counter That Counts From (111 To 000) If Current State Is 101 The Next State Will Be
|
111
|
110
|
010
|
None Of Given Options
|
D |
| CS302 |
For A Gated D-Latch If En=1 And D=1 Then Q(T+1) =
|
0
|
1
|
Q(T)
|
Invalid
|
D |
| CS302 |
For A Gated D-Latch If En=1 And D=1 Then Q(T+1) = ___________
|
0
|
1
|
Q(T)
|
Invalid
|
B |
| CS302 |
For A Positive Edge-Triggered J-K Flip-Flop With Both J And K High The Outputs Will If The Clock Goes High
|
Toggle
|
Set
|
Reset
|
Not Change
|
A |
| CS302 |
For A Standard Sop Expression A Is Placed In The Cell Corresponding To The Product Term (Minterm) Present In The Expression
|
0
|
1
|
X
|
None Of The Given Options
|
B |
| CS302 |
Generally The Power Dissipation Of Devices Remains Constant Throughout Their Operation
|
Ttl
|
Cmos 3.5 Series
|
Cmos 5 Series
|
Power Dissipation Of All Circuits Increases With Time
|
A |
| CS302 |
Given The State Diagram Of An Up/Down Counter We Can Find __________
|
The Next State Of A Given Present State
|
The Previous State Of A Given Present State
|
Both The Next And Previous States Of A Given State
|
The State Diagram Shows Only The Inputs/Outputs Of A Given States
|
A |
| CS302 |
Half-Adder Logic Circuit Contains Xor Gates
|
0
|
2
|
4
|
6
|
B |
| CS302 |
How Many Data Select Lines Are Required For Selecting Eight Inputs?
|
|||||
| CS302 |
How Many Data Select Lines Are Required For Selecting Eight Inputs?
|
1
|
2
|
3
|
4
|
C |
| CS302 |
If A Circuit Suffers “Clock Skew “ Problem The Output Of Circuit Can’T Be Guarantied
|
True
|
False
|
B | ||
| CS302 |
If An S-R Latch Has A 1 On The S Input And A 0 On The R Input And Then The S Input Goes To 0 The Latch Will Be
|
Set
|
Reset
|
Invalid
|
Clear
|
A |
| CS302 |
If S=1 And R=0 Then For Positive Edge Triggered Flip-Flop Q(T+1) = Select Correct Option
|
0
|
1
|
Invalid
|
Input Is Invalid
|
A |
| CS302 |
If S=1 And R=0 Then Q(T+1) = ___________ For Positive Edge Triggered Flip-Flop
|
0
|
1
|
Invalid
|
Input Is Invalid
|
B |
| CS302 |
If S=1 And R=1 Then Q(T+1) = ___________ For Negative Edge Triggered Flip-Flop
|
0
|
1
|
Invalid
|
Input Is Invalid
|
C |
| CS302 |
If The Fifo Memory Output Is Already Filled With Data Then __________
|
It Is Locked; No Data Is Allowed To Enter
|
It Is Not Locked; The New Data Overwrites The Previous Data
|
Previous Data Is Swapped Out Of Memory And New Data Enters
|
None Of Given Options
|
D |
| CS302 |
If The S And R Inputs Of The Gated S-R Latch Are Connected Together Using A Gate Then There Is Only A Single Input To The Latch. The Input Is Represented By D Instead Of S Or R (A Gated D-Latch)
|
And
|
Or
|
Not
|
Xor
|
C |