CS101 532 CS201 225 CS301 232 CS302 174 CS304 192 CS401 224 CS402 258 CS403 228 CS408 113 CS411 121 CS502 249 CS504 268 CS601 679 CS604 381 CS605 261 CS607 184 CS609 230 CS610 300 CS614 100 CS703 65
Code Question Option A Option B Option C Option D Answer
CS302 If Two Adjacent 1S Are Detected In The Input The Output Is Set To High 0011 0101 1100 1010 A
CS302 If Two Adjacent 1S Are Detected In The Input The Output Is Set To High. Input Combinations Will Be 0011 0101 1100 1010 A
CS302 In __________ All The Columns In The Same Row Are Either Read Or Written Sequential Access Mos Access Fast Mode Page Access None Of Given Options C
CS302 In __________ Outputs Depend Only On The Combination Of Current State And Inputs Mealy Machine Moore Machine State Reduction Table State Assignment Table A
CS302 In __________ Outputs Depend Only On The Current State Mealy Machine Moore Machine State Reduction Table State Assignment Table B
CS302 In __________ Q Output Of The Last Flip-Flop Of The Shift Register Is Connected To The Data Input Of The First Flip-Flop Of The Shift Register Moore Machine Meally Machine Johnson Counter Ring Counter D
CS302 In A Sequential Circuit The Next State Is Determined By __________ And State Variable Current State Current State Flip-Flop Output Current State And External Input Input And Clock Signal Applied C
CS302 In A State Diagram The Transition From A Current State To The Next State Is Determined By Current State And The Inputs Current State And Outputs Previous State And Inputs Previous State And Outputs A
CS302 In Asynchronous Digital Systems All The Circuits Change Their State With Respect To A Common Clock True False B
CS302 In Asynchronous Transmission When The Transmission Line Is Idle ___________ It Is Set To Logic Low It Is Set To Logic High Remains In Previous State State Of Transmission Line Is Not Used To Start Transmission B
CS302 In Case Of Cascading Integrated Circuit Counters The Enable Inputs And Rcoof The Integrated Circuit Counters Allow Cascading Of Multiple Counters Together True False B
CS302 In Designing Any Counter The Transition From A Current State To The Next Sate Is Determined By Current State And Inputs Only Inputs Only Current State Current State And Outputs A
CS302 In Designing Any Synchronous Counter A Modulus Number Is Used Which Determine The Number Of............ Used In A Counter Registers Flip Flops Counters Latches B
CS302 In Nor Gate Based S-R Latch If Both S And R Inputs Are Set To Logic 0 The Previous Output State Is Maintained True False A
CS302 In Order To Synchronize Two Devices That Consume And Produce Data At Different Rates We Can Use ___________ Read Only Memory Fist In First Out Memory Flash Memory Fast Page Access Mode Memory B
CS302 In The Following Statement( Z Pin 20 Istype „Reg.Invert";) The Keyword “Reg.Invert” Indicates __________ An Inverted Register Input An Inverted Register Input At Pin 20 Active-High Registered Mode Output Active-Low Registered Mode Output D
CS302 In The Q Output Of The Last Flip-Flop Of The Shift Register Is Connected To The Data Input Of The First Flip-Flop Moore Machine Meally Machine Johnson Counter Ring Counter C
CS302 Karnaugh Map Is Used In Designing A Clock A Counter An Up/Down Counter All Of The Above D
CS302 Lut Is Acronym For ___________ Look Up Table Local User Terminal Least Upper Time Period None Of Given Options A
CS302 Nand Gate Is Formed By Connecting ___________ And Gate And Then Not Gate Not Gate And Then And Gate And Gate And Then Or Gate Or Gate And Then And Gate A