|
CS302
|
5-Bit Johnson Counter Sequences Through States
|
7
|
10
|
32
|
25
|
B
|
|
CS302
|
The Total Amount Of Memory That Is Supported By Any Digital System Depends Upon
|
The Organization Of Memory
|
The Structure Of Memory
|
The Size Of Decoding Unit
|
The Size Of The Address Bus Of The Microprocessor
|
D
|
|
CS302
|
At T0 The Value Stored In A 4-Bit Left Shift Was “1”. What Will Be The Value Of Register After Three Clock Pulses?
|
2
|
4
|
6
|
8
|
D
|
|
CS302
|
A Full-Adder Has A Cin = 0. What Are The Sum (<Private Type=Pict;Alt=Sigma> ) And The Carry (Cout) When A = 1 And B = 1?
|
if = 0 Cout = 0
|
if = 0 Cout = 1
|
if = 1 Cout = 0
|
if = 1 Cout = 1
|
B
|
|
CS302
|
3-To-8 Decoder Can Be Used To Implement Standard Sop And Pos Boolean Expressions
|
True
|
False
|
|
|
A
|
|
CS302
|
Nor Gate Can Be Used To Perform The Operation Of And Or And Not Gate
|
True
|
False
|
|
|
A
|
|
CS302
|
The 74Hc163 Is A 4-Bit Synchronous Counter.It Has..............Parallel Data Inputs Pins
|
2
|
4
|
6
|
8
|
B
|
|
CS302
|
The Alternate Solution For A Demultiplexer-Register Combination Circuit Is ___________
|
Parallel In / Serial Out Shift Register
|
Serial In / Parallel Out Shift Register
|
Parallel In / Parallel Out Shift Register
|
Serial In / Serial Out Shift Register
|
B
|
|
CS302
|
In Asynchronous Transmission When The Transmission Line Is Idle ___________
|
It Is Set To Logic Low
|
It Is Set To Logic High
|
Remains In Previous State
|
State Of Transmission Line Is Not Used To Start Transmission
|
B
|
|
CS302
|
A Multiplexer With A Register Circuit Converts ___________
|
Serial Data To Parallel
|
Parallel Data To Serial
|
Serial Data To Serial
|
Parallel Data To Parallel
|
B
|
|
CS302
|
The __________ Input Overrides The __________ Input
|
Asynchronous Synchronous
|
Synchronous Asynchronous
|
Preset Input (Pre) Clear Input (Clr)
|
Clear Input (Clr) Preset Input (Pre)
|
A
|
|
CS302
|
A Modulus-14 Counter Has Fourteen States Requiring__________
|
14 Flip Flops
|
14 Registers
|
4 Flip Flops
|
4 Registers
|
C
|
|
CS302
|
The 4-Variable K-Map Has Rows And ___________ Columns Of Cells
|
2 2
|
2 4
|
4 2
|
4 4
|
D
|
|
CS302
|
A Counter Is Implemented Using Three (3) Flip-Flops Possibly It Will Have __________ Maximum Output Status
|
3
|
7
|
8
|
15
|
C
|
|
CS302
|
If S=1 And R=0 Then For Positive Edge Triggered Flip-Flop Q(T+1) = Select Correct Option
|
0
|
1
|
Invalid
|
Input Is Invalid
|
A
|
|
CS302
|
A Negative Edge-Triggered Flip-Flop Changes Its State When ____________________
|
Enable Input (En) Is Set
|
Preset Input (Pre) Is Set
|
Low-To-High Transition Of Clock
|
High-To-Low Transition Of Clock
|
D
|
|
CS302
|
The Terminal Count Of A 4-Bit Binary Counter In The Down Mode Is__________
|
0000
|
0011
|
1100
|
1111
|
D
|
|
CS302
|
The Ansi/Ieee Standard 754 Defines A __________Single-Precision Floating Point Format For Binary Numbers
|
8-Bit
|
16-Bit
|
32-Bit
|
64-Bit
|
C
|
|
CS302
|
Demultiplexer Converts Data To __________ Data
|
Parallel Data Serial Data
|
Serial Data Parallel Data
|
Encoded Data Decoded Data
|
All Of The Given Options
|
B
|
|
CS302
|
Which One Of The Following Is Not A Valid Rule Of Boolean Algebra?
|
A + 1 = 1
|
A = A
|
A.A = A
|
A + 0 = A
|
B
|