CS101
532
CS201
225
CS301
232
CS302
174
CS304
192
CS401
224
CS402
258
CS403
228
CS408
113
CS411
121
CS502
249
CS504
268
CS601
679
CS604
381
CS605
261
CS607
184
CS609
230
CS610
300
CS614
100
CS703
65
| Code | Question | Option A | Option B | Option C | Option D | Answer | |
|---|---|---|---|---|---|---|---|
| CS302 | The Four Outputs Of Two 4-Input Multiplexers Connected To Form A 16-Input Multiplexer Are Connected Together Through A 4-Input __________ Gate | And | Or | Nand | Xor | B | |
| CS302 | The Glitches Due To Race Condition Can Be Avoided By Using A __________ | Gated Flip-Flops | Pulse Triggered Flip-Flops | Positive-Edge Triggered Flip-Flops | Negative-Edge Triggered Flip-Flops | D | |
| CS302 | The High Density Flash Memory Cell Is Implemented Using __________ | 1 Floating-Gate Mos Transistor | 2 Floating-Gate Mos Transistors | 4 Floating-Gate Mos Transistors | 6 Floating-Gate Mos Transistors | A | |
| CS302 | The Hours Counter Is Implemented Using __________ | Only A Single Mod-12 Counter Is Required | Mod-10 And Mod-6 Counters | Mod-10 And Mod-2 Counters | A Single Decade Counter And A Flip-Flop | D | |
| CS302 | The Low To High Or High To Low Transition Of The Clock Is Considered To Be A(N) __________ | State | Edge | Trigger | One-Shot | B | |
| CS302 | The Minimum Time For Which The Input Signal Has To Be Maintained At The Input Of Flip-Flop Is Called Of The Flip-Flop | Set-Up Time | Hold Time | Pulse Interval Time | Pulse Stability Time (Pst) | B | |
| CS302 | The Operation Of J-K Flip-Flop Is Similar To That Of The Sr Flip-Flop Except That The J-K Flip-Flop __________ | Doesn’T Have An Invalid State | Sets To Clear When Both J = 0 And K = 0 | It Does Not Show Transition On Change In Pulse | It Does Not Accept Asynchronous Inputs | A | |
| CS302 | The Or Gate Performs Boolean __________ | Multiplication | Subtraction | Division | Addition | D | |
| CS302 | The Output Of An And Gate Is One When | All Of The Inputs Are One | Any Of The Input Is One | Any Of The Input Is Zero | All The Inputs Are Zero | A | |
| CS302 | The Output Of An Xnor Gate Is 1 When __________ I) All The Inputs Are Zero Ii) Any Of The Inputs Is Zero Iii) Any Of The Inputs Is One Iv) All The Inputs Are One | I Only | Iv Only | I And Iv Only | Ii And Iii Only | D | |
| CS302 | The Output Of An Xor Gate Is Zero (0) When __________ I) All The Inputs Are Zero Ii) Any Of The Inputs Is Zero Iii) Any Of The Inputs Is One Iv) All The Inputs Are One | I Only | Iv Only | I And Iv Only | Ii And Iii Only | C | |
| CS302 | The Output Of The Expression F=A.B.C Will Be Logic __________ When A=1 B=0 C=1 | Undefined | One | Zero | No Output As Input Is Invalid | C | |
| CS302 | The Power Consumed By A Flip-Flop Is Defined By __________ | P = Icc X Rcc | P = Vcc X Rcc | P = Vcc X Icc | P = Mcc X Vcc | C | |
| CS302 | The Power Dissipation Pd Of A Logic Gate Is The Product Of The | Dc Supply Voltage And The Peak Current | Dc Supply Voltage And The Average Supply Current | Ac Supply Voltage And The Peak Current | Ac Supply Voltage And The Average Supply Current | A | |
| CS302 | The Process Of Converting The Analogue Signal Into A Digital Representation (Code) Is Known As __________ | Strobing | Amplification | Quantization | Digitization | C | |
| CS302 | The Prom Consists Of A Fixed Non-Programmable __________ Gate Array Configured As A Decoder | And | Or | Not | Xor | A | |
| CS302 | The Sequence Of States That Are Implemented By A N-Bit Johnson Counter Is | N+2 (N Plus 2) | 2N (N Multiplied By 2) | 2N (2 Raise To Power N) | N2 (N Raise To Power 2) | B | |
| CS302 | The Simplest And Most Commonly Used Decoders Are The Decoders | N To 2N | (N-1) To 2N | (N-1) To (2N-1) | N To 2N-1 | A | |
| CS302 | The Storage Cell In Sram Is | A Flip –Flop | A Capacitor | A Fuse | A Magnetic Domain | B | |
| CS302 | The Synchronous Counters Are Also Known As Ripple Counters | True | False | B |