CS101 532 CS201 225 CS301 232 CS302 174 CS304 192 CS401 224 CS402 258 CS403 228 CS408 113 CS411 121 CS502 249 CS504 268 CS601 679 CS604 381 CS605 261 CS607 184 CS609 230 CS610 300 CS614 100 CS703 65
Code Question Option A Option B Option C Option D Answer
CS401 The First Instruction Of “Com” File Must Be At Offset: 0X0010 0X0100 0X1000 0X0000 B
CS401 The First Instruction Of “Com” File Must Be At Offset: 0X0010 0X0100 0X1000 0X0000 B
CS401 The Iapx88 Processor Supports __________ Modes Of Memory Access. 5 6 7 8 C
CS401 The Iapx888 Architecture Consists Of Register. 12 14 16 18 C
CS401 The Iapx888 Architecture Consists Of Register. 12 14 16 18 C
CS401 The Input Frequency Of The Programmable Interval Timer (Pit) Is Fixed Depends On Processor Clock Variable Depends On Hardware Attached A
CS401 The Instruction Adc Has__________ Operand(S) 0 1 2 3 D
CS401 The Instruction Used To Read A Character From The Keyboard Port Is In Al 0X60 Out Al 0X60 In Al 0X80 Out Al 0X80 A
CS401 The Interrupt Mask Register Which Can Be Used For Selectively Enabling Or Disabling Interrupts Is Associated With Port 19 Port 20 Port 21 Port 22 C
CS401 The Maximum Parameters A Subroutine Can Receive (With The Help Of Registers) Are 6 7 8 9 B
CS401 The Memory Address Always Move From Processor To Memory Memory To Processor Memory To Peripheral Peripheral To Processor A
CS401 The Number Of Bits In A Cell Is Called The Cell Width.__________ Define The Memory Completely Cell Width And Number Of Cells Cell Number And Width Of The Cells Width Height A
CS401 The Number Of Bits Required To Access 1Mb Of Memory Are 16 Bits 20 Bits 32 Bits Depends On The Processor Architecture D
CS401 The Number Of Pins In A Parallel Port Connector Are? 20 25 30 35 B
CS401 The Operation Of Cmp Is To Subtract Source From Destination Subtract Destination To From Source Add 1 To The Destination ?Add Source And Destination A
CS401 The Parallel Port Connector Is Called? Db-25 Bd-25 Db-24 Bd-24 A
CS401 The Physical Address Of Idt( Interrupt Descriptor Table) Is Stored In Gdtr Idtr Ivt Idtt B
CS401 The Physical Address Of The Stack Is Obtained By Ss:Si Combination Ss:Sp Combination Es:Bp Combination Es:Sp Combination B
CS401 The Prevalent Convention In Most High Level Languages Is Stack Clearing By The Caller Callee Ret Stack B
CS401 The Process Of Sending Signals Back And Forth Is Called Activity Hand-Shaking Interruption Time Clicking D