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CS302
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For A Standard Sop Expression A Is Placed In The Cell Corresponding To The Product Term (Minterm) Present In The Expression
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0
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1
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X
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None Of The Given Options
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B
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CS302
|
Given The State Diagram Of An Up/Down Counter We Can Find __________
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The Next State Of A Given Present State
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The Previous State Of A Given Present State
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Both The Next And Previous States Of A Given State
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The State Diagram Shows Only The Inputs/Outputs Of A Given States
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A
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CS302
|
The Encoder Is Used As A Keypad Encoder
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2-To-8 Encoder
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4-To-16 Encoder
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Bcd-To-Decimal
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Decimal-To-Bcd Priority
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D
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CS302
|
The Prom Consists Of A Fixed Non-Programmable __________ Gate Array Configured As A Decoder
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And
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Or
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Not
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Xor
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A
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CS302
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When The Both Inputs Of Edge-Triggered J-K Flop-Flop Are Set To Logic Zero
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The Flop-Flop Is Triggered
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Q=0 And Q’=1
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Q=1 And Q’=0
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The Output Of Flip-Flop Remains Unchanged
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B
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CS302
|
A 4-Bit Binary Up/Down Counter Is In The Binary State Zero. The Next State In The Down Mode Is__________
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0001
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1111
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1000
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1110
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B
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CS302
|
For A Gated D-Latch If En=1 And D=1 Then Q(T+1) = ___________
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0
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1
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Q(T)
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Invalid
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B
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|
CS302
|
Karnaugh Map Is Used In Designing
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A Clock
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A Counter
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An Up/Down Counter
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All Of The Above
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D
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CS302
|
The Domain Of The Expression Ab Cd + Ab + C D + B Is
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A And D
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B Only
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A B C And D
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None Of These
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C
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CS302
|
__________ Is One Of The Examples Of Synchronous Inputs
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J-K Input
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En Input
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Preset Input (Pre)
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Clear Input (Clr)
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A
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|
CS302
|
Nor Gate Is Formed By Connecting ___________
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Or Gate And Then Not Gate
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Not Gate And Then Or Gate
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And Gate And Then Or Gate
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Or Gate And Then And Gate
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A
|
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CS302
|
Consider A=1 B=0 C=1. A B And C Represent The Input Of Three Bit Nand Gate The Output Of The Nand Gate Will Be
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Zero
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One
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Undefined
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No Output As Input Is Invalid
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B
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|
CS302
|
If S=1 And R=0 Then Q(T+1) = ___________ For Positive Edge Triggered Flip-Flop
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0
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1
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Invalid
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Input Is Invalid
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B
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CS302
|
For A Down Counter That Counts From (111 To 000) If Current State Is 101 The Next State Will Be
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111
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110
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010
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None Of Given Options
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D
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